Gav's World : My CV

Curriculum Vitae for Gavin Cameron

Address available on request

Education:

1992 to 1996	Napier University, Edinburgh	BSc Electronic and Electrical Engineering
1986 to 1992	Knox Academy, Haddington	1 CSYS, 5 Higher Grades, 7 O / Standard Grades

Also studied for MSc in Electronics and Communication Engineering at Napier University, but did not complete the course as nothing useful was being gained.

Hardware Expertise:

Currently using VHDL for design and verification (Tools: HDL Designer, Modelsim), FPGA/CPLD Synthesis (Tools: Leonardo Spectrum, Xilinx Place and Route), Schematic Capture (Tools: Mentor Graphics), PCB Design and board level simulation (Tools: Mentor Graphics). Have used a wide array of Logic Analysers, Oscilloscopes, Pattern Generators, PROM programmers and In-Circuit Emulators for test, validation and integration activities. Also previously used embeded microcontrollers, Abel for PAL programming and Max Plus+ for CPLD based design activity.

Software Expertise:

Have used a combination of C and Shell scripting to analyse test data and data parsing. C and Assembler have been used to perform fault finding tests on faulty processor cassettes. Other experiences include Pascal and Basic.

Employment Details:

September 1992 to Present

SELEX Galileo
Crewe Toll,
Ferry Road,
Edinburgh,
EH5 2XS.

Joined as a trainee engineer and studied for BSc on a day release basis, graduated and was retained.

Captor Tranche II Processor Unit: Designing part of the Compact Communications Processor cassette, which allows the new processor architecture to be backwards compatible with the old system. Primarily based on Xilinx FPGAs, the work focuses around VHDL, creating re-usable blocks and pre-fabrication test benches. Also responsible for one of the two PCBs that the cassette is assembled from. This involves high speed PCB design considerations: signal integrity, EMC, board level simulation. Will also be involved with full cassette integration and system level integration activities.

Captor Tranche I Processor Unit: Designed and validated test equipment for 3 data processing cassettes for the production series of radar processor. Designs primarily focused on JTAG based testing, using VHDL, targeting Xilinx CPLDs. Previously debugged damaged A / C-model cassettes using both hardware and software techniques.

Captor System Integration Lab: Designed several items of test equipment to aid in the integration activities of the radar system. These include military specification bus monitors (e.g. Stanag 3838 / 3910), cooling pack monitors, emulators, active break-out boxes and a data recording interface. Was tasked with all aspects of designs: schematic capture, PAL/CPLD design & programming, mechanical drawings, PCB layout, purchasing of components and assembly of some PCBs.

Further Details:

Keen fan of the Linux operating system as a platform for engineering tools and have set up several servers / workstations on the company network. Hobbies include performance cars (driving and modifying), DVD collecting, beer festivals and other social events.